Optimization Technique for FB/TB Assignment in PD-SOI Digital CMOS Circuits
نویسندگان
چکیده
This work presents a technique for reducing the total leakage current in PD-SOI combinational circuits by mixing floating-body and tied-body transistors in the same circuit. Basic gate characterization data are first presented, and then used as part of a static timing analysis based optimization algorithm. Results obtained from a number of benchmark circuits show a decrease of up to 86% in total leakage current.
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تاریخ انتشار 2003